Non-dissipative snubber circuit apparatus

ABSTRACT

A dual-switch transformer-coupled switching regulator is provided with a non-dissipative snubber circuit arrangement wherein the resonant elements thereof include an inductor serially connected between two capacitors through a diode switch. The snubber has two other diode switches that are connected on mutually exclusive ones of the same sides of the capacitors that are connected to the inductor. Each of the last two mentioned diode switches connects the respective aforementioned side of the particular capacitor to the outer main terminal of a mutually exclusive one of the dual transistor switches of the regulator. The other side of the particular capacitor is connected to the other main terminal of the other one of the dual transistor switches. The arrangement minimizes any deleterious effects caused when the dual switches are being switched.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention is related to non-dissipative snubber circuit apparatusand more particular to non-dissipative snubber circuit apparatus fordual-switch transformer-coupled switching regulators.

2. Description of the Prior Art

Protection of transistor power switches in switching regulators by acurrent snubber circuit is well known in the art; see, for example,"Designing Non-Dissipative Current Snubbers For Switched ModeConverters", E. C. Whitcomb, Proceedings of POWERCON® 6, May 2-4, 1979,1st Printing April 1979 (pre-conference edition), pp B1-1 to B1-6; "BaseDrive Considerations in High Power Switching Transistors", D. Roark,TRW® Power Semiconductors Application Note, No. 120(1/75), pp 1 to 11;and "Schottky Rectifiers Shine in Low-Voltage Switchers", R. Patel,Electronic Design, Dec. 10, 1981, pp 149 to 154.

More particularly, snubber circuits, or snubbers as they are sometimessimply referred to in the art, have found general acceptance inprotecting switching regulators that use only a single transistor powerswitch, or a pair of transistor power switches that operate in a pushpull mode, i.e. alternately or out of phase. These include snubbers ofboth the well known dissipative and non-dissipative types.

However, heretofore, in the prior art of which I am aware, fordual-switch transformer-coupled switching regulators wherein two inphase transistor switches are in series coupled relationship with theswitching transformer, only dissipative snubber types have been used.Heretofore, a non-dissipative type has not been used with these lastmentioned kind of switching regulators, herein sometimes referred to asa dual switch switching regulator, because in general of the circuitcomplexity required for implementation and the resultant problemsassociated with operating the two transistors in phase.

SUMMARY OF THE INVENTION

It is an object of this invention to provide non-dissipative snubbercircuit apparatus that is readily implemented with dual switchtransformer coupled switching regulators.

It is another object of this invention to provide non-dissipativesnubber circuit apparatus of the aforementioned kind that is simple andreliable.

According to one aspect of the present invention, in dual-switchtransformer-coupled switching regulator circuit apparatus, there isprovided in combination therewith snubber circuit apparatus. Theregulator circuit apparatus has a pair of first and second semiconductorswitch means operable in phase, and transformer means. The input windingof the transformer means is coupled in series between the first andsecond switch means at predetermined first and second junctions,respectively. The series coupled pair of switch means and input windingare adapted for series connection between the positive and negativeterminal means of a predetermined dc supply at predetermined third andfourth junctions, respectively. The regulator circuit apparatus furtherhas third and fourth semiconductor switch means. The third switch meansis coupled between the first junction and the fourth junction. Thefourth switch means is coupled between the second junction and the thirdjunction.

In the snubber circuit apparatus there is provided first and secondcapacitor means, and inductor means. Each of the capacitor means has apair of first and second electrodes. The second electrode of thecapacitor means is coupled to the first junction of the regulatorapparatus, and the second electrode of the second capacitor means iscoupled to the second junction. First diode means couples the inductormeans between the first electrodes of the first and second capacitormeans. Second diode means couples the first electrode of the firstcapacitor means to the fourth junction. Third diode means couples thefirst electrode of the second capacitor means to the third junction.

The foregoing and other objects, features and advantages of theinvention will be apparent from the more particular description of thepreferred embodiment of the invention, as illustrated in theaccompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a schematic view of the preferred embodiment of thenon-dissipative snubber circuit apparatus of the present invention in aknown dual switch transformer coupled switching regulator partiallyshown in block form;

FIGS. 2A-2B are idealized waveform timing diagrams of certain voltageand current waveforms associated with the circuitry of FIG. 1; and

FIG. 3 is an idealized waveform timing diagram illustrating waveforms ofthe switching losses associated with the power switches of the apparatusof FIG. 1 under different conditions.

In the Figures, like elements are designated with similar referencenumbers.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, there is shown a dual-switchtransformer-coupled switching regulator generally indicated by thereference numeral 1. In the preferred embodiment, the regulator 1 hasdual semiconductor switch means, shown by way of example assubstantially two identical NPN type transistor power switches 2 and 3arranged in common emitter configurations. Preferably, the switches 2and 3 have fast switching times. Switches 2 and 3 are in series coupledrelationship with the hereinafter described switching transformer means.

The series coupled pair of dual switches 2 and 3 are adapted to beseries coupled between the positive and negative terminals 4 and 5 of anunregulated dc supply 6 at the input terminals or junctions 37 and 38.Thus, in the preferred embodiment, the collector and emitter oftransistor switches 2 and 3, respectively, are connected directly to theterminals 4 and 5, respectively. Supply 6 includes a source 6a ofunregulated dc voltage Vb and an associated low impedance input filtercapacitor 6b. Source 6a may be a battery or other appropriate dc sourcewhich directly provides voltage Vb, hereinafter sometimes referred to asthe bulk voltage. Alternatively, source 6a may be an appropriaterectified ac source which provides bulk voltage Vb, for example, from anac line supply.

The switching transformer means 7, herein sometimes referred to simplyas the switching transformer, of the preferred embodiment has a magneticcore 7a and single-ended input and output windings 8 and 9,respectively. Input winding 8, and hence transformer 7, is seriallycoupled between the two switches 2 and 3 at the junctions 10 and 11,respectively. Thus, in the preferred embodiment of FIG. 1, winding 8 isserially connected between the emitter of transistor switch 2 and thecollector of transistor switch 3. The output winding 9 is coupled viarectifier and filter circuits 12 and 13, respectively, to the outputterminals 14 and 15, which in turn are connected across the load RL.

Preferably, switches 2 and 3 are opened and closed substantially inphase by a feedback control circuit 16 which provides a common controlor driver signal to the control inputs of switches 2 and 3. Thus, in thepreferred embodiment, the common control signal is provided at each ofthe paired outputs 17-18 and 19-20 of circuit 16 which are connected tothe respective base-emitter inputs of switches 2 and 3, respectively.The input of circuit 16 is connected across the output terminals 14 and15 via conductor 21 and common ground 22 and senses the regulated outputvoltage at the output 14-15. Such feedback control circuits, which arewell known in the art, provide a pulse train control signal withpredetermined switching frequency and on/off duty cycle characteristicscommensurate with the regulation desired for the dc output at terminals14 and 15 and can adjust at least one of the characteristics' parametersto compensate for any deviations in the level of the sensed outputvoltage from a predetermined reference level and thereby maintain thedesired dc output. Such deviations may, for example, be due to changesin the load RL, and/or input Vb, etc. Demagnetizing diode switches 23and 24 are connected between the emitters and between the collectors,respectively, of switches 2 and 3.

The switching regulator 1 is preferably configured for a forwardoperational mode in which case transformer 7 has the dot polarityindicated in solid form in FIG. 1 for the windings 8 and 9. Accordingly,the rectifier 12, illustrated schematically as diode 25, isappropriately poled as shown by its solid outline form in FIG. 1.Alternatively, the regulator 1 may be configured for a flybackoperational mode by locating the diode 25 in the other leg of thewinding 9 as shown by the dash outline form 25'. Depending on theparticular operational mode, the filter 13 is modified accordingly.Thus, in the forward operational mode, filter 13 is an LC type with thechoke inductor thereof being connected between diode 25 and terminal 14and the capacitor being connected across terminals 14 and 15 in a mannerwell known to those skilled in the art. On the other hand, in theflyback operational mode, only a capacitor, which is connected acrossthe terminals 14 and 15, is required as the winding 9 acts as the chokeas is well known to those skilled in the art. In the forward operationalmode, it should be understood that, as is customary, there is associatedwith the filter 13 an appropriately poled free wheeling diode, notshown, which is connected across the input of filter 13.

The basic principles of transformer coupled switching regulators and oftheir forward and flyback operational modes are well known to thosefamiliar with the art. Briefly and with respect to the dual switchtransformer coupled switching regulator 1 of FIG. 1, in the forward modewhen switches 2 and 3 are closed, i.e. are on, energy is transferredfrom winding 8 to winding 9. More particularly, diode 25 is forwardbiased, the aforementioned free wheeling diode is reversed biased, andthe current in winding 9 passes through the aforementioned choke windingof filter 13 and divides into the two parallel branches which are formedby the aforementioned capacitor of filter 13 and the load RL. In doingso, the current in the capacitor branch is used to recharge the filtercapacitor to the desired regulated dc output voltage level, and thecurrent in the load branch is used to supply the load at the desiredregulated dc output voltage level. When switches 2 and 3 are opened,diode 25 is reversed biased, the free wheeling diode is forward biased,and the energy stored in the capacitor of filter 13 in coaction with thechoke inductor of filter 13 and free wheeling diode is delivered throughthe load RL at a rate sufficient to maintain the desired regulated dcoutput voltage level.

In the flyback operational mode, when switches 2 and 3 are closed, thediode 25' is reversed biased and the energy is stored in winding 8.There is no transfer of energy from winding 8 to winding 9 during thisperiod. However, energy previously stored in the capacitor of filter 13,which has no inductor as previously explained, is delivered to the loadRL at a rate sufficient to maintain the desired regulated dc outputvoltage level. When switches 2 and 3 are opened, diode 25' is forwardbiased. The energy stored in the winding 8 is transferred to winding 9,the latter also doubling as a choke as aforementioned. The current inwinding 9 passes through the conducting diode 25' and divides into thetwo parallel branches formed by the capacitor of filter 13 and the loadRL. The current in the capacitor branch recharges the capacitor to thedesired regulated dc output voltage level, and the current in the loadbranch is used to supply the load RL at the desired regulated dc outputvoltage level.

Generally, the forward operational mode is used for high powerapplications and the flyback operational mode for low powerapplications. As is well known to those skilled in the art, the nominallevel of the regulated output at terminals 14-15 depends inter alia onthe parameters selected for the turns ratio of windings 8 and 9, theon/off duty cycle and the switching frequency.

According to the principles of the present invention, non-dissipativesnubber circuit apparatus is provided in combination with a dual-switchtransformer-coupled switching regulator. In FIG. 1, the preferredembodiment of the non-dissipative snubber circuit apparatus of thepresent invention is generally indicated by reference numeral 26. Thecircuit apparatus or snubber 26 has a pair of capacitors 27 and 28 andan inductor 29. The capacitors 27 and 28 each have a pair of electrodesdesignated 30 and 31. Electrode 31 of capacitor 27 is coupled tojunction 10, and electrode 31 of capacitor 28 is coupled to junction 11.As such, electrodes 31 of capacitors 27 and 28 are coupled to theemitter and collector, respectively, of transistor switches 2 and 3,respectively. A diode switch 32 couples the inductor 29 between theelectrodes 30 of capacitors 27 and 28. A second diode switch 33 coupleselectrode 30 of capacitor 27 to the junction 38 between the emitter oftransistor switch 3 and the negative terminal 5 of supply 6. Anotherdiode switch 34 couples electrode 30 of capacitor 28 to the junction 37between the collector of the other transistor switch 2 and the positiveterminal 4 of supply 6. As can readily be seen, snubber 26 is thuscoupled across the switch terminals, to wit: collector and emitterelectrodes, of each of the switches 2 and 3. Preferably, an anti-ringingcircuit, i.e. capacitor 35 and resistor 36, is provided across theinductor 29.

The operation of the circuitry of FIG. 1 in the preferred forwardoperational mode will next be described with reference to the waveformsA-S of FIGS. 2A-2B. By way of example and/or for purposes ofexplanation, it will be assumed that transistor switches 2 and 3 areideal and simultaneously turn off. The reference characters v and i,which appear parenthetically alongside the ordinate axes associated withthe waveforms A-S of FIGS. 2A-2B, are used to designate voltage andcurrent waveform types, respectively, shown thereat. The waveforms A-Sin FIGS. 2A-2B are plotted on a common time axis.

As aforementioned, switches 2 and 3 are adapted to be turned on and off,i.e. closed and opened, substantially in phase by the common controlsignal, not shown, at the output 17-20 of circuit 16. In the preferredembodiment, the control signal is a base drive signal appearing as anadjustable recurring pulse train which produces a switching frequency1/T with a closed switch time (Tc) to open switch time (To) ratio Tc/To,cf. FIG. 2A. Moreover, in the preferred embodiment, the output signal atterminals 14-15 is regulated by varying the ratio Tc/To and maintaininga constant switching frequency 1/T. Hence, the switching period T isalso a constant k, where:

    T=Tc+To=k.

Waveforms A-K, FIG. 2A, pertain to the switching regulator 1. The basecurrents IB2 and IB3 of transistor switches 2 and 3, respectively, areshown by the same waveform A for sake of simplicity. Waveforms B and Fare the collector currents IC2 and IC3, respectively, and waveforms Cand G are the collector-to-emitter voltages Vce2 and Vce3, respectively,of respective switches 2 and 3. The voltage across winding 8 and thecurrent associated with it are shown by waveforms D and E, respectively.Waveforms H and I are the voltages at junctions 10 and 11, respectively,taken with respect to ground. The currents associated with diodes 23 and24 are illustrated by the waveforms J and K, respectively.

It is to be understood, as is apparent to those skilled in the art, thecurrent waveform E is the algebraic composite of certain waveforms ofwhich one is the waveform associated with the magnetizing current IM oftransformer 8. The magnetizing current IM builds up during themagnetizing period and returns to the zero level during thedemagnetizing period in accordance with well known principles.Preferably, the magnetizing and demagnetizing periods are substantiallyequal. For sake of clarity and purposes of explanation, the waveform ofthe magnetizing current IM is plotted commonly with the waveform E usingthe same set of axes as shown in FIG. 2A. Thus, the periods t0-t6 andt6-t8 are the magnetizing and demagnetizing periods, respectively,associated with the waveform of the magnetizing current IM. During theperiod t0-t7, the magnetizing current IM is shown in dash-dot outlineform but because during the period t7-t8 it becomes superimposed withthe waveform E it hence is shown in solid outline form thereat.

Waveforms L-S, FIG. 2B, pertain to the snubber 26. Waveforms L and P arethe respective charge/discharge currents associated with capacitors 27and 28, respectively, and waveforms M and Q are the correspondingvoltages taken across capacitors 27 and 28, respectively. Likewise,waveform N is the current waveform associated with inductor 29 andwaveform O is the corresponding voltage taken across inductor 29. Thecurrents associated with diode switches 33 and 34 are shown by waveformsR and S, respectively.

It is assumed for purposes of explanation that at time t0 a turn-onperiod Tc commences. In response to the base drive signal, the basecurrents of switches 2 and 3 at the beginning of the turn-on period Tcrapidly rise to their respective staturated condition levels +IB fromtheir just previous cutoff condition levels, i.e. zero level 0, cf.waveform A.

Moreover, at time t0, as switches 2 and 3 become conductive, the dcsupply 6 begins to supply current. The current leaves terminal 4 ofsupply 6, passes through the closed switch 2, divides at junction 10into two current branch parallel circuit paths next to be describedwhich are rejoined at junction 11, and returns through closed switch 3to terminal 5 of supply 6. One of the aforementioned two paths isthrough the winding 8 of the switching transformer 7 of regulator 1. Theother path is through the series connected resonant elements 27, 29, 28and forward biased diode switch 32 of snubber 26. As is apparent tothose skilled in the art, diode switches 33 and 34, as well as switches23 and 24, are reversed biased at time t0.

During the rise time period t0-t1, the current in winding 8 rises at arate which is substantially dependent on the magnetic inductance of thetransformer 7 and leakage inductance of the aforementioned chokewinding, not shown, of filter 13, cf. waveform E. The current in winding8 rises from its zero level 0 to the level I1, which is dependent uponthe input voltage Vb divided by the product of the reflected impedanceacross winding 8 and the square of the turns ratio of the windings 8 and9. The voltage across winding 8, i.e. waveform D, likewise rises rapidlyduring the period t0-t1 from the zero level 0 to the level +Vt.

During the time period t1-t4, i.e. the remainder of the turn-on timeperiod Tc, the current in winding 8 continues to rise but at a slowerrate which is dependent on the magnetic inductance of transformer 7 andthe self-inductance of the aforementioned choke winding of filter 13,reaching a level I2 at time t4, at which time the base drive signal fromcontrol circuit 16 begins the turn off period To for switches 2 and 3.The corresponding voltage, waveform D, remains substantially at the +Vtlevel during the corresponding period t1-t4.

Concurrently, at time t0 as switches 2 and 3 become conductive, thecurrent in the other one of the aforementioned two branch circuitsstarts to flow in a sinusoidal manner through the series resonantcircuit 27-29 of snubber 26. Thus, as shown by waveform L, N, or P, FIG.2B, the snubber current rises from its zero level 0 at time t0 to a peakIp at time t2 during the first quarter period t0-t2 of the resonantcycle, and then falls back to its zero level 0 at time t3 during thesecond quarter period t2-t3 of the resonant cycle. As the snubbercurrent passes through the capacitors 27 and 28 during the period t0-t3,the snubber capacitors 27 and 28 are charged thereby and rise from theirrespective zero voltage levels 0 at time t0 to their positive +Vb/2levels at time t2, and continue to rise thereafter to their positivelevels +Vb at time t3 as shown by the waveforms M and Q, respectively.

The same snubber current passes through the snubber inductor 29 duringthe period t0-t3 as shown by waveform N. Moreover, as shown by waveformO, the voltage across inductor 29 during the period t0-t3 is inquadrature relationship with the snubber current and inverse phaserelationship with the respective voltages M and Q of the snubbercapacitors 27 and 28. Thus, the voltage across inductor 29 risessubstantially instantaneously from its zero level 0 to level +Vb at timet0 and begins to fall, crossing the zero level at time t2, and continuesto fall till reaching the -Vb level at time t3.

During the period t0-t2, inductor 29 has a polarity of + to - from leftto right as viewed facing FIG. 1 and the snubber current, which ischarging the snubber capacitors 27 and 28, is substantially provided bysupply 6. During the period t2-t3, the polarity reverses across theinductor 29 and inductor 29 provides the charging current for thesnubber capacitors 27 and 28 continuing to charge them to theirrespective levels +Vb.

The second half of the resonant cycle is effectively blocked by therectifier action of diode 32 at time t3. More specifically, as shown bywaveform O, as the inductor voltage at time t3 attempts to rise to thepositive level +Vb, it reverses its polarity thereby reverse biasing thediode 32 and preventing discharge of capacitors 27 and 28 throughinductor 29 for the remainder of the period Tc, as well as thesubsequent period To. Any ringing in the snubber current at time t3 ismitigated by the anti-ringing circuit 35-36.

Thus, during the period t0-t3, the current waveform B or F, whichrepresents the current passing through each of the transistor switches 2and 3, is the algebraic composite of the current waveform E associatedwith the current in winding 8 and the current waveform L, N, or Oassociated with the current in snubber 26. During the time period t3-t4,no current passes through snubber 26 and the switches 2 and 3 passcurrent only through the winding 8.

At time t4, the turn-off period To of the switching cycle begins inresponse to the change in the base drive signal, not shown, applied totransistor switches 2 and 3 from control circuit 16. As a result, thebase currents, cf. waveform A, of switches 2 and 3 at time t4 rapidlyfall to respective cutoff condition levels -IB and switches 2 and 3begin to turn-off simultaneously. However, due to the effects of storagetime of the transistor switches 2 and 3, the current through winding 8,as well as its constituent magnetizing current, continues to rise duringthe interval t4-t5, cf. corresponding waveforms B, E and F. During thissame interval, the voltage across winding 8 remains at level +Vt, cf.waveform D.

At time t5, the storage time of the transistor switches 2 and 3 ends,and the current, waveforms B and F, through switches 2 and 3 dropsrapidly from the level I3 at time t5 to the zero level 0 at time t6during the period t5-t6. Correspondingly, the base currents, waveform A,return to the zeo level 0 at time t6, and switches 2 and 3 are fullyturned off.

Moreover, during the period t5-t7, the collector-to-emitter voltagesVce2 and Vce3 of switches 2 and 3 rise from their saturated conditionlevel 0 at time t5 to their cutoff condition level +Vb at time t7 asshown by waveforms C and G. As a result, during the corresponding periodt5-t7, the voltage with respect to ground at junction 10 goes from level+Vb to level 0, and the voltage with respect to ground at junction 11goes from level 0 to level +Vb, cf. waveforms H and I.

During the period t5-t6, the transistor switches 2 and 3 are stillconducting and are in the process of being fully turned off by time t6.However, because the inductance of the filter choke 7 of filter circuit13 tends to oppose the change in current, the curent in winding 8 doesnot drop as rapidly and consequently drops to the level I4 at time t6,cf. waveform E.

At time t6, switches 2 and 3 are fully turned off, and the current inwinding 8 rapidly drops to the level I5 at time t7 as shown by waveformE. It should be noted that, during the period t5-t7, the voltage acrosswinding 8 drops from level +Vt, passes through the zero level 0 at timet6, and reaches its negative level -Vt at time t7 as shown by waveformD.

At time t7, diode switches 23 and 24 become forward biased. During thenext period t7-t8, the magnetizing current in the winding 8 is returneddirectly to the supply 6 and stored in the filter capacitor 6b throughthe closed switches 23 and 24, cf. waveform E, J or K. The voltageacross winding 8 remains at the level -Vt during the period t7-t8.

At time t8, the magnetizing current IM reaches the zero level 0 andhence there is no conduction through winding 8. As a result, thevoltage, waveform D, across it goes from its level -Vt at time t8 to thezero level 0 at time t9 and remains at the zero level 0 for the rest ofthe period To, i.e. until the beginning of the next switching period Tat time t10.

Referring now to the snubber circuit 26, as aforementioned during theperiod t3-t5, as well as the remainder of the period t5-t10, diode 32 isreversed biased. At time t5, the voltage at junction 10 begins to dropfrom its +Vb level as shown by waveform H. The resultant voltage changeat junction 10 in turn is transmitted through the capacitor 27 makingits electrode 30, and hence the cathode of diode 33, more negative thanthe anode of diode 33 whereupon diode 33 becomes forward biased. Asimilar action occurs with respect to the diode 34 as the result of thevoltage at junction 11 beginning to rise from its -Vb level at time t5as shown by waveform I. Accordingly, the resultant voltage change atjunction 11 in turn is transmitted through the capacitor 28 making itselectrode 30 and hence the anode of diode 34 more positive than thecathode of diode 34 whereupon diode 34 becomes forward biased.

As a result, during the period t5-t6, capacitors 27 and 28 rapidly beginto discharge mainly through a series circuit path beginning arbitrarilyfor sake of description at electrode 31 of capacitor 27, and thence insequence through winding 8, capacitor 28, diode 34, filter capacitor 6b,diode 33 and terminating at the other electrode 30 of capacitor 27.Discharge through switches 2 and 3 is substantially negligible duringthe corresponding period t5-t6 due to the switches 2 and 3 presenting ahigher impedance to the inductive energy stored in the transformer 7than the impedance of capacitors 27,28. When the switches 2 and 3completely turn off at time t6, the capacitors 27 and 28 continue toabsorb the inductive energy from the transformer 7 and discharge throughthe last mentioned circuit path. Hence, as shown by the currentwaveforms L and P, the capacitors 27 and 28 are completely dischargedduring the period t5-t7 and their corresponding voltage waveforms dropfrom their respective levels +Vb to zero levels 0, at which times diode33 and 34 become reverse biased. At time t10, the next switching cyclebegins.

Should the switches 2 and 3 not turn off at the same time, the regulator1 and snubber 26 are not adversely effected. For example, if switch 3should begin to turn-off before switch 2, diode 34 becomes forwardbiased and capacitor 28 begins to discharge toward the zero voltagelevel 0 through diode 34, the still fully on switch 2, and winding 8.The source current continues to flow through elements 2, 8 and 3. Whenswitch 3 is fully turned off and if switch 2 is still fully on, theinductive current of winding 8 and the discharge current of capacitor 28flow in the closed series loop of switch 2, winding 8, and diode 34.

When capacitor 28 is fully discharged, if the switch 2 has begun to turnoff or when it subsequently begins to turn off, diode 34 becomes reversebiased and diodes 33 and 24 become forward biased. As result, capacitor27 begins to discharge through a main circuit path which includescapacitor 27, winding 8, diode 24, filter capacitor 6b and diode 33.Concurrently, the inductive current of winding 8 passes through anotherloop, to wit: switch 2, winding 8 and diode 24.

When switch 2 fully turns off, capacitor 27 continues to dischargethrough aforementioned loop which includes elements 27, 8, 24, 6b and33. Thereafter, when capacitor 27 becomes discharged, diode 33 isreverse biased and diode 23 forward biased. The magnetizing current thenpasses through the closed loop which includes winding 8, diode 24,filter capacitor 6b, and diode 23. Upon termination of the magnetizingcurrent, diodes 23 and 24 are reverse biased and no current flows in theregulator 1 or snubber 26 until the next switching cycle.

As is readily apparent to those skilled in the art, the circuitoperation is slightly modified for intermediate cases which fall betweenthe two extreme cases, i.e. between the case where switches 2 and 3 turnoff simultaneously and the case where one switch remains temporarilyfully on after the other is turned fully off as, for example, the casejust previously described. Thus, for sake of simplicity, the circuitoperation description for such an intermediate case is omitted herein.In any case, the efficacy of the apparatus of FIG. 1 is not adverselyeffected.

Referring to FIG. 3, for example, current and voltage waveforms 40 and41 thereof correspond to the current and voltage waveforms of switch 2or 3, i.e. waveforms B and C of switch 2 or waveforms F and G of switch3, during the transient period t5-t7 that the switches 2 and 3 areturning off simultaneously. For simultaneous cutoff, the currentwaveforms B and F are hence superimposed as shown by the waveform 40 ofFIG. 3, and likewise the corresponding voltage waveforms C and G arealso superimposed as shown by the waveform 41 of FIG. 3. Therefore, forsimultaneous cutoff, the switching losses, i.e. the product of thecurrent and voltage waveforms 40 and 41 as represented by the shadedarea A1 formed under the intersection of the two curves 40 and 41between time t5 and t6, are substantially equal. However, if one of theswitches should be delayed from starting turn off for some time delay,e.g. td, after the other switch turns off at time t5, nevertheless theswitching losses of the delayed switch are still substantially equal tothe switching losses of the aforementioned other switch. Thus, in FIG.3, waveforms 40' and 41' represent the current and voltage waveformsassociated with the delayed switch during its transient period from timet5+td to time t7+td. The switching losses associated with the delayedswitch during this period are represented by the shaded area A2 underthe intersection of the two curves 40' and 41' between time t5+td andtime t6+td and is substantially equal to the switching losses of theother switch as represented by the area A1 under its associated curves40 and 41 between time t5 and t6.

The apparatus of circuit 1 is readily implemented in discreet,integrated, and hybrid circuitry. Typical parameters for the apparatusof FIG. 1 are given in the following table.

TABLE

Switching Frequency 1/T--30 KH.±10%

Bulk Voltage Vb--300 v.±30%

Capacitors 27, 28, each--0.01 uf.

Inductor 29--400 uh.

Transformer leakage inductance--100 uh.

In some applications, it may be desirable that one of the switches 2, 3be favored to deliberately turn off after the other has turned off sothat one switch will have greater switching losses than the other. Insuch a case, this may be accomplished, for example, by merely changingthe value of an appropriate one of the capacitors 27 and 28. Also, oneor both of the switches 2 and 3 can have one or more additional switchesconnected in parallel therewith for greater current switching capacityor the like as is well known to those skilled in the art. Also, whilethe invention has been described with particular NPN transistor types,it may also be implemented with PNP types with an appropriate adjustmentof polarity. Other modifications to the apparatus of FIG. 1 include theuse of other types of driver circuits in lieu of the feedback typecircuit 16.

Thus, while the invention has been described with reference to apreferred embodiment thereof, it will be understood by those skilled inthe art that various changes in form and details may be made withoutdeparting from the scope of the invention.

I claim:
 1. In dual-switch transformer-coupled switching regulatorcircuit apparatus, said regulator circuit apparatus having:a pair offirst and second semiconductor switch means operable in phase,transformer means having an input winding coupled in series between saidfirst and second switch means at predetermined first and secondjunctions, respectively, said series coupled pair of switch means andinput winding being adapted for series connection between the positiveand negative terminal means of a predetermined dc supply atpredetermined third and fourth junctions, respectively, and third andfourth semiconductor switch means, said third switch means being coupledbetween said first junction and said fourth junction, and said fourthswitch means being coupled between said second junction and said thirdjunction,the combination therewith of non-dissipative snubber circuitapparatus, said snubber circuit apparatus comprising: first and secondcapacitor means, each of said capacitor means having a pair of first andsecond electrodes, said second electrode of said first capacitor meansbeing coupled to said first junction, and said second electrode of saidsecond capacitor means being coupled to said second junction, inductormeans, first diode means for coupling said inductor means between saidfirst electrodes of said first and second capacitor means, second diodemeans for coupling said first electrode of said first capacitor means tosaid fourth junction, and third diode means for coupling said firstelectrode of said second capacitor means to said third junction.
 2. Thecombination according to claim 1 wherein said snubber circuit apparatusfurther comprises an anti-ringing circuit connected across said inductormeans.
 3. The combination according to claim 1 wherein said regulatorcircuit apparatus further has control means for periodically opening andclosing said first and second switch means.
 4. The combination accordingto claim 3 wherein said regulator circuit apparatus is of the forwardoperational mode type.
 5. In dual-switch transformer-coupled switchingregulator circuit apparatus, said regulator circuit apparatus having:apair of first and second power transistors operable in phase, each ofsaid transistors having base, emitter and collector electrodes,respectively, a transformer having an input winding connected in seriesbetween the emitter electrode of said first transistor and the collectorelectrode of said second transistor, said collector electrode of saidfirst transistor and said emitter electrode of said second transistorbeing connectable across the positive and negative terminals of apredetermined dc supply, first and second diodes, said first diode beingconnected between said emitter electrodes of said first and secondtransistors, and said second diode being connected between the collectorelectrodes of said first and second transistors, and driver meansconnected to said base electrodes for periodically turning saidtransistors on and off,the combination therewith of non-dissipativesnubber circuit apparatus, said snubber circuit apparatus comprising:first and second capacitors, each of said capacitors having a pair offirst and second electrodes, said second electrode of said firstcapacitor being connected to said emitter electrode of said firsttransistor, and said second electrode of said second capacitor beingconnected to said collector electrode of said second transistor, aninductor, a third diode connecting said inductor between said firstelectrodes of said first and second capacitors, a fourth diode forconnecting said first electrode of said first capacitor to said emitterelectrode of said second transistor, and a fifth diode for connectingsaid first electrode of said second capacitor to said collectorelectrode of said first transistor.
 6. The combination according toclaim 5 wherein said regulator circuit apparatus is of the forwardoperational mode type.
 7. The combination according to claim 5 whereinsaid snubber circuit apparatus further comprises an anti-ringing circuitconnected across said inductor.
 8. The combination according to claim 5wherein said first and second transistors are NPN types.
 9. Thecombination according to claim 5 wherein said regulator circuitapparatus has a switching frequency of 30 KiloHertz±10%.
 10. Thecombination according to claim 5 wherein the capacitance of each of saidcapacitors is substantially 0.01 uf and the inductance of said inductoris substantially 400 mh.